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| This invention relates to a vector processor architecture providing vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which manipulate operands associated with the vector registers. The data size defined by an instruction determines the number of the data elements in a vector register and the number of parallel operations performed to complete the instruction. This patented technology can be applied to a media processor processing not only the currently commercialized coding/decoding data formats but also newly developing data formats.accordance aspect the DSP set general-purpose vector registers fixed partitioned separate data elements user selectable number stored depends 32-byte divided thirty two 8-bit sixteen 16-bit eight 32-bit Selection type instruction associated execution path performs parallel operations indicated Instructions processor scalar operands manipulate multiple computing power exemplary co-processor interface flow control load/store logic/arithmetic combine corresponding generate mix various quantities |
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