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| This invention relates to multiprocessors and particularly to systems and methods for coordinating or synchronizing parallel execution of separate program threads. The multiple processing units constitute a general-purpose or control processor and a vector processor which has a single-instruction-multiple-data (SIMD) architecture so that multiple parallel processing units in the vector processor all complete an instruction simultaneously and do not require software synchronization. The control processor controls the vector processor and creates a fork in a program flow by starting the vector processor. An instruction set for the control processor includes special instructions that enable the control processor to access registers of the vector processor, start or halt execution by the vector processor, and test flags written by the vector processor to indicate completion of tasks. The two processors then execute separate program threads in parallel until the control processor stops the vector processor, an exception is encountered, or the vector processor completes its program thread and enters an idle state. An instruction set for the vector processor includes special instructions that interrupt the first processor to indicate a task is complete. A register coupled to and accessible by both processors stores a state bit indicating whether the vector processor is running or idle. The control processor can synchronize the separate program threads by executing a loop which polls the state bit. When the state bit indicates the vector processor is idle, the general-purpose processor can process results from the vector processor and restart the vector processor.accordance embodiment integrated multiprocessor two asymmetric program control sometimes referred herein executes continuous thread start stop execution second co-processor processors share extended register set facilitates communication synchronization access co-processors registers initialize later started circuitry first hardware simplified instruction sets architectures implements instructions reading writing accessing starting interrupting signal completion setting state flag indicate idle poll mechanism completed tasks Additionally polled either whether necessary precursor continuing polling synchronized stopping special tests general-purpose vector single-instruction-multiple-data efficient computational power inefficiently implementing functions handles relatively narrower path dual-processor large units flexibility separate threads simplicity software implemented |
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