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Design and Verification Test Method for Programmable Logic Devices
Honeywell, a leader in aerospace engine and controls technology, provides an automated, 3-phase process for efficient design, implementation, and verification of programmable logic devices (PLDs) at the device pin level. Each phase, with associated sub-steps, may be accomplished in parallel with other phases/sub-steps. This novel design and verification test method satisfies today's rapid design cycles, stringent certification requirements, and the increased reliability demanded by complex aerospace engine controls. Honeywell's verification test method provides for simulation testing in the design phase, which is leveraged in the hardware verification environment. The actual hardware implementation is tested with the exact same set of test vectors as the simulation models, thereby allowing for traceability. Notably, this cost effective technology is comprehensive, yet less labor intensive than competing methods. The innovation verification process is compatible with FAA and JAA safety critical hardware requirements.Various certification authorities imposed stringent requirements verifying operation programmable logic devices (PLDs)

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