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| AIST invented a field-effect transistor. According to this invention, as the formation of the gate electrode and upper gate electrode is self-aligning and only one photolithography step is required, the fabrication process is simplified and leads to the easy commercial fabrication with reducing costs at the same time. Also, since the formation of the two gate electrodes self-align, errors arising from mask misalignment are eliminated, the product yield is improved. In addition, the self-alignment allows to achieve a shorter gate length using the same lithographic feature dimension, the transistor performance is improvedFIG shows cross-sectional views source drain electrodes side semiconductor conduction channel illustrate structure self-aligning dual gate field-effect transistor the steps fabricating shown n-channel silicon SOI (Semiconductor Insulator) layer trench extends down surface buried insulation substrate single crystal oxide recrystallized upper 10 polycrystalline 1(a) fabricated conventional reference resistance concentration n-type p-type case p-channel transistors coexist selective impurities region portion contact left 1(b) either Next removed extending applied completely exposed divided two regions 3a 3b formation material 1(c) thickness insulated next starting epitaxially growing time grown increased amount electrically pn junction difficult even metal planar lamination 1(d) insulates walls oxidized Simultaneously oxidation prevention nitride beforehand 1(e) top connect 25 [FIG 1(h)] 26 self-aligned seed solid phase growth amorphous deposited Amorphous simultaneously recrystallization 1(f) inside 1(g) 11 covering entire level leaving just Finally portions element whereby adjacent elements obtaine separated |
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