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Power supply voltage of MIS LSIs has been reduced as the channel length of the MIS transistor in the LSI has been scaled (reduced). However, program voltage (write or erase voltage) of nonvolatile memories, especially used for NAND applications, remained at a high value around 17 volts, even if the power supply voltage of logic circuits in the LSI is reduced to a value less than 1 volt. This high value of program voltage is one of obstacles to the realization of nonvolatile memory with less than low tens of nm design rule.

In the nonvolatile memories comprising a stack of a gate/a memory means/a semiconductor region and when the memory means is a multilayer insulator into which memory charges are injected from the semiconductor by a high electric field applied between the gate and the semiconductor region, reduction of the program voltage can be realized by the reduction of the thickness of the multilayer insulator. However, retention time of the charge stored in it is also shortened. This constraint cannot be solved by a flat plate stack structure of conventional planar devices (as shown in Fig. 1).

Scientists with AIST proposed a principle and structure to overcome the constraint. The structure comprises a first semiconductor member having a generally columnar shape having an operative length and a first surface along the operative length, said generally columnar shape defining a cross section that would appear when cut in a direction perpendicular to the operative length; a memory means provided on the first surface of the first semiconductor member, the memory means at least partially surrounding the first semiconductor member at a location at which said cross section is defined; and a gate provided on the memory means as shown in Fig. 2. An equivalent radius r of the cross section is set to be smaller than a quivalent oxide film thickness tm of the memory means for the reduced programming voltage with better retention. For details see below.

Benefits Summary

1) a nonvolatile nano-memory smaller than tens nm beyond the scaling rule 2) with low program voltage even with a memory means of a multilayer insulator of conventional materials and/or thickness, 3) and with longer retention, 4) optionally with quantized multi-level memorization. more

IP Summary

This technology is supported by 1 US patent, 1 Japanese patent and 1 European patent. more

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