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Our client has developed an innovative solution for frequency, phase and time synchronization in packet based networks at a receiving client/slave. Completely IEEE 1588v2 standard compliant, the solution focuses on the issue of slave clock design. More specifically, the solution enables time or frequency synchronization using appropriate clock offset and skew estimation techniques and a digital phase locked loop (DPLL) at the client/slave receiving IEEE 1588 PTP synchronization signals from a Master clock (which can be GrandMaster or Boundary Clock).

The IP addresses these challenges through:

  1. Estimating clock offset and skew, particularly from two-way exchange of PTP messages between a master and a slave device.
  2. A skew and offset adjustable local clock for regenerating the master time and frequency at the slave device.
  3. A mechanism incorporated with the estimation algorithm which reduces the ‘effective’ dynamic range of the packet delay variation (PDV) and the clock errors they contribute to

The prototype is a client or slave device that provides high accuracy time synchronization (less than 1 microsecond) and frequency synchronization (less 50 parts-per-billion) capabilities over a range of different packet network configurations.

Our client’s synchronisation solutions can be used in a number of network configurations.